1. Field of the Invention
The invention relates generally to semiconductor memory devices and, more particularly, relates to structures for shortening the testing time thereof.
2. Description of the Background Art
With development of semiconductor techniques, storage capacity of semiconductor memory devices has been remarkably increased. The storage capacity has been rapidly increased by four times about every three years. Such semiconductor memory devices, from the point of view of quality assurance, require a test to see if they operate normally after being manufactured. A time period (testing time) required for this test has been sharply (exponentially) increased with the increase in the storage capacity of semiconductor memory devices. The increase in the testing time causes an increase in the cost not only of a semiconductor memory device itself but also of a system employing the same. Therefore, the introduction of techniques for shortening the testing time becomes essential and indispensable. A multibit parallel testing scheme is one of such testing time shortening techniques, in which memory cells of a plurality of bits are simultaneously tested.
FIG. 1 is a diagram schematically showing the overall structure of a conventional semiconductor memory device with a multibit parallel testing function. In FIG. 1, the conventional semiconductor memory device includes a memory cell array 100 including a plurality of memory cells arranged in a matrix of rows and columns, an address buffer 102 for receiving an externally applied address A0 to An and generating an internal address, a row decoder 104 for selecting a corresponding row of memory cell array 100 in accordance with an internal row address from address buffer 102, a column decoder 106 responsive to an internal column address from address buffer 102 for generating a signal for selecting a corresponding column of memory cell array 100, and an I.multidot.O gate 110 responsive to a column select signal from this column decoder 106 for connecting the selected column within memory cell array 100 to a common data bus 108.
Memory cell array 100 is divided into four blocks MB1, MB2, MB3 and MB4. 1 bit from each of the memory cell blocks MB1 to MB4, i.e., memory cells of 4 bits in total are simultaneously selected and connected to common data bus 108. Row decoder 104 selects one row from each of memory cell blocks MB1 to MB4. Column decoder 106 generates a column select signal for selecting one column from each of memory cell blocks MB1 to MB4. Common data bus 108 includes four data bus lines 108a, 108b, 108c and 108d provided corresponding to each memory cell block so as to transmit data of 4 bits in parallel.
The semiconductor memory device further includes a write circuit 112 which is activated in response to an internal write instructing signal W at the time of writing data, for receiving externally applied write data Din and generating internal write data, a block decoder 114 for decoding a block designation signal from address buffer 102 and selecting one block of memory cell blocks MB1 to MB4, a read out circuit 116 for receiving read out data from the memory cell block selected by this block decoder 114 and generating external read out data Dout, and a test circuit 118 for simultaneously receiving memory cell data of 4 bits read on the common data bus 108, effecting a predetermined operational processing on the same, and generating a signal indicating whether or not the memory cells of 4 bits are normal.
Test circuit 118 is activated in response to a test mode instructing signal T and carries out a prescribed operational processing with respect to the data of 4 bits on common data bus 108. Read out circuit 116 is set to an output high impedance state at the time of the test mode in response to an inverted signal /T of the test mode instructing signal. Block decoder 114 connects internal data bus 120 to four common data bus lines 108a to 108d in response to a logical product signal W.multidot.T of an internal write instructing signal W indicating data writing at the time of the test mode and a test mode instructing signal T. Data writing is carried out on a 4-bit basis at the time of the test mode. This semiconductor memory device has a .times.1 bit structure in which input/output of data is carried out on a 1-bit basis. The operation thereof will now be described.
The operation at the time of a normal mode will be described. Address buffer 102 generates an internal row address and an internal column address in response to an externally applied address A0 to An. Row decoder 104 decodes this internal row address and selects one row from each of memory cell blocks MB1 to MB4 of memory cell array 100. Column decoder 106 receives and decodes an internal column address except, for example, 2 least significant bits therein and generates a signal for selecting one column from each of memory cell blocks MB1 to MB4. I.multidot.O gate 110 connects one column from each of memory cell blocks MB1 to MB4 to common data bus lines 108a to 108d, respectively, in response to the column select signal from column decoder 106. As a result, the memory cells of 4 bits selected by row decoder 104 and column decoder 106 are connected to common data bus lines 108a to 108d.
At the time of writing data, write circuit 112 is activated in response to the internal write instructing signal W, generates internal write data from the externally applied write data Din and transmits the same to internal data bus 120. Block decoder 114 decodes a block address including, for example, 2 least significant bits in the internal column address from address buffer 102 and connects one of the data bus lines 108a to 108d to internal data bus 120. As a result, data is written into a memory cell of the block designated by block decoder 114 among the simultaneously selected memory cells of 4 bits.
At the time of reading data, the internal write instructing signal W is in an inactive state and write circuit 112 is brought to an output high impedance state. Read out circuit 116 amplifies read out data transmitted from one common data bus line selected by the block decoder 114 and generates external read out data Dout. As a result, reading of data of a memory cell of 1 bit is completed. This read out circuit 116 may operate at the time of data writing or it may be set to an output disable state or a high impedance state at the time of data writing. As for test circuit 118, at the time of a normal operation mode, the test mode instructing signal T is in an inactive state and the output thereof is set to a high impedance state.
The operation at the time of the test mode will now be described. At the time of the test mode, external write data Din of a predetermined logical value ("1" or "0") is applied. The internal write data generated from write circuit 112 at the time of the test mode is applied to block decoder 114. Block decoder 114 transmits data on the internal data bus 120 onto the four common data bus lines 108a to 108d in response to the signal W.multidot.T in an active state. As a result, the same data is simultaneously written into the memory cells of 4 bits which have been selected in the same way at the time of the normal operation mode. When this operation is carried out with respect to all the memory cells within memory cell array 100, the same data is written into all the memory cells of memory cell array 100.
In the functional test of the semiconductor memory device, a test is conducted to see if each memory cell within memory cell array 100 exactly holds the applied data.
After writing of the same data into all the memory cells within memory cell array 100 is completed, in the same way as at the time of the normal operation mode, data of memory cells of 4 bits is read out from each of memory cell blocks MB1 to MB4 and transmitted onto the four common data bus lines 108a to 108d. Test circuit 118 is activated in response to the test mode instructing signal T, effecting a prescribed operational processing on the memory cell data of 4 bits on the common data bus lines 108a to 108d and supplies a signal indicating the result of the processing. The output from test circuit 118 is provided as external data Dout. A defective bit (for example, inversion of the stored data) and so on in the semiconductor memory device is detected by monitoring the external data Dout on the outside.
At the time of the test mode, read out circuit 116 is set to the output high impedance state in response to the inverted signal /T. In the structure shown in FIG. 1, there may be a multiplexer for receiving the outputs of test circuit 118 and read out circuit 116, selectively passing either of them in response to the test mode instructing signal T and supplying external data Dout. A variety of operational functions conducted by test circuit 118 have been proposed.
FIG. 2 is a diagram schematically showing the structure of a test circuit 118 for implementing a test function of "1/0/Hi-Z" scheme. In FIG. 2, test circuit 118 includes an AND type gate circuit G1 for receiving data D0 to D3 of 4 bits on a common data bus 108 and receiving a test mode instructing signal T, an inverter circuit G2 for inverting the test mode instructing signal T, an NOR type gate circuit G3 for receiving the data D0 to D3 of 4 bits on common data bus 108 and the output of inverter circuit G2, a first output transistor OT1 for receiving the output of gate circuit G1 at its gate, and a second output transistor OT2 for receiving the output of gate circuit G3 at its gate.
Gate circuit G1 supplies a signal of "H" when all the applied signals are at "H". Gate circuit G3 supplies a signal of "H" when all the applied signals are at "L". Output transistors OT1 and OT2 each are turned on when a signal applied to the gate attains "H". First output transistor OT1 charges the output node NA to "H" of the operating power supply potential Vcc when it is turned on. The second output transistor OT2 discharges the output node NA to "L" level of the potential Vss level being the ground potential, for example, when it is turned on. Let the potential "H" correspond to logic "1" and potential "L" correspond to logic "0". The operation of test circuit 118 shown in FIG. 2 will now be described.
At the time of the test mode, the test mode instructing signal T is set to "H" and the output of inverter circuit G2 attains "L". When all the read out data D0 to D3 of 4 bits are at logic "1", the output potential of gate circuit G1 attains "H" and the output potential of gate circuit G3 attains "L". The first output transistor OT1 is turned on, the second output transistor OT2 is turned off, and the output node NA is charged to the potential "H". As a result, output data Dout of logic "1" is obtained.
When all the read out data D0 to D3 of 4 bits are at logic "0", the output potential of gate circuit G1 attains "L", and the output potential of gate circuit G3 attains "H". The first output transistor OT1 is thereby turned off, the second output transistor OT2 is turned on, the output node NA is discharged to "L" of the potential Vss level and output data Dout of logic "0" is generated.
When the 4 bit memory cell data D0 to D3 includes data of logic "0" and "1" in a mixed manner, the output potentials of gate circuits G1 and G3 both attain "L". In this case, output transistors OT1 and OT2 are both turned off and the output node NA is brought to a high impedance state. The same data has been written into all the memory cells within memory cell array 100. Accordingly, if there is a defective bit in the simultaneously selected memory cells of 4 bits, the output data Dout is brought to the high impedance state. If the logical values of the memory cell data D0 to D3 of 4 bits coincide with each other, output data Dout of the same logical value as that of this memory cell data is obtained. If the data D0 to D3 of the simultaneously selected memory cells of 4 bits all have the logic inverted with respect to that of the write data, the output data Dout takes a logical value opposite to an expected value (data to be read out) and the defect can be detected.
FIG. 3 is a diagram schematically showing a test circuit having a test function according to a "coincidence/non-coincidence" scheme. In FIG. 3, a test circuit 118 includes a coincidence detection circuit G4 for receiving read out data D0 to D3 of 4 bits and a transmission gate TM which is turned on in response to a test mode instructing signal T, for passing the output of coincidence detection circuit G4. In the structure of test circuit 118 shown in FIG. 3, if all the logical values of the read out data D0 to D3 of 4 bits coincide with each other, logic "1" is supplied from coincidence detection circuit G4. The 4 bit read out data D0 to D3 includes data of logic "1" and "0" in a mixed manner, logic "0" is supplied from coincidence detection circuit G4.
Data of the same logic has been written into the all the memory cells in memory cell array 100. Therefore, if the output data Dout attains logic "0", it means a malfunction of the semiconductor memory device.
A specific example of a structure for shortening the testing time of a semiconductor memory device can be found, for example, in M. Kumanoya, "A 90 ns 1 Mb DRAM with multi-bit test mode", 1985 IEEE, ISSCC, Digest of Technical Papers, p240. The article by Kumanoya discloses a method of simultaneously testing memory cells of 4 bits in a dynamic random access memory (DRAM) of an address multiplexing scheme with 1M (mega) word .times.1 bit structure.
While a parallel test of memory cells of 4 bits is shown in the description of the above-mentioned prior art, this method can be basically extended to a method of simultaneously testing more memory cells. For this extension, however, it is necessary to provide the same number of common data bus lines as that of memory cells to be simultaneously tested. Normally, an amplifying circuit such as a preamplifier for amplifying a signal potential is provided for the common data bus lines. Therefore, in order to simultaneously test as many memory cells as possible for reducing the testing time, it is necessary to add common data bus lines and amplifying circuits, causing a problem of an increase in the chip area and the power consumption.
Other than a semiconductor memory device in which input/output of data is carried out through common data bus lines, there is a semiconductor memory device in which a data write bus and a data read bus are provided separately in order to read out data at high speed. Even in this separated I/O structure type memory device, a read out data amplifying circuit is also provided for the data read out bus and the same problem as described above is caused. One example of an I/O separate-type semiconductor memory device is described in Y. Nakagome et al., "A 1.5 V Circuit Technology for 64 Mb DRAMs", IEEE, the precedings of 1990 Symposium on VLSI circuits, pp. 17-18, Feb. 1990.
Considering all of the testing time and the chip area and power consumption, practically, memory cells of 4 bits in a DRAM of 1M bits, memory cells of 8 bits in a DRAM of 4M bits, and memory cells of 16 bits in a DRAM of 16M bits are generally tested simultaneously. As seen from the relationship between the storage capacity of the semiconductor memory device and the number of bits of memory cells to be simultaneously tested, practically, it is difficult to linearly increase the number of memory cells to be simultaneously tested in proportion to the increase in the storage capacity, and the testing time has been disadvantageously increased sharply with the increase in the storage capacity. For example, while the storage capacity of a DRAM of 16M bits is 16 times as large as that of a DRAM of 1M bits, the number of memory cells which can be simultaneously tested is only increased by 4 times. Accordingly, if simply calculated, the testing time of the DRAM of 16M bits is about 4 times as long as that of the DRAM of 1M bits.